High density memory systems such as cache systems in semiconductor apparatuses consume large amounts of power when transmitting data over signal lines as a result of capacitive loading on those signal lines. For example, a single logical (or memory) bank in a high density cache system of a semiconductor apparatus may include 16 megabytes (MB) of memory comprising 32 macros (or collections) of 512K Static Random Access Memory (SRAM). The power consumed when transmitting data across the signal lines with 32 macros is almost four times greater than the dynamic operating power of 1 macro.
FIG. 1 is a block diagram illustrating the transmission of data between two devices in a typical semiconductor apparatus, such as a system on a chip (SoC). As shown, a data bus 104 is disposed between a first device such as a memory device 102, and a second device such as a processor 106. Output from the memory device 102 is transmitted to the processor 106 via the data bus 104, which as illustrated is a 3-bit data bus having a set of signal lines 124—one for each of the 3-bits (D<0:2>). The data bus 104 may include repeaters such as a set of buffers 122 to regenerate signals on each of the set of signal lines 122 of the data bus 104.
One problem associated with the layout of the devices in FIG. 1 is that if each signal line of the set of signal lines 122 in the data bus 104 is not sufficiently spaced apart, their close proximity to each other will cause interference and crosstalk on the signal lines that will distort and cause error in the transmitted data. As a result, more space is typically allocated in the semiconductor apparatus to position the signal lines, with a tradeoff of having reduced usable space in exchange for reduced errors.
Another problem associated with the layout of the devices in FIG. 1 is that interference and crosstalk on the set of signal lines 122 can cause the communicated data to randomly change. For example, the communicated data can randomly change from 000 to 111, or any combination in between as one or more of set of signal lines 122 in the data bus 104 may randomly change state from 0 to 1 or from 1 to 0.
Power is consumed each time one of the set of signal lines 122 changes state, such as when a state changes from 0 to 1, because the signal line needs to be driven to an opposite state. In the architecture of FIG. 1, to communicate a series of 3-bit words, an average of 1.5 bits of the 3 bits will change state because a change from one word to another requires at least one bit to change. Consequently, a significant amount of power is consumed during the transmission of data directly over the set of signal lines 122 of the data bus 104 as shown in FIG. 1.
Accordingly, there is a need for an approach for reducing power when transmitting data between devices in a semiconductor apparatus.